
U.S.
Patent
Apr.
10,
2007
Sheet
6
0f
19
US
7,203,135
B2
FIG.6
CPU
=
A
E
CHANNEL
CONTROL
w
501
'
PORTION
MEMORY
_
DISK
CONTROL
w
'
PORTION
502
DATA
READ
PROCESS
’—\/601
DATA
CONTROLLER
506
II
DATA
WRITE
PROCESS
"\J
602
II
RAID
CONFIGURATION
TABLE
’"\/603
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